1. Field of the Invention
The present invention relates to a circuit substrate, which includes a plurality of wiring patterns, and a manufacturing method of the circuit substrate. Here, each of the plurality of wiring patterns is stacked on another through a dielectric member and is electrically connected with one another.
2. Description of Related Art
Conventionally, Japanese Unexamined Patent Publication No. 2001-36253 discloses a circuit substrate, in which an influence of a generated stress is limited. Here the stress is generated due to a difference of coefficients of thermal expansion between the circuit substrate and an electric device mounted to the circuit substrate. FIG. 5 is a sectional view of a schematic structure of the circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253.
The circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253 includes a body substrate 100 and a film substrate 200. The body substrate 100 includes dielectric layers 110 made of a dielectric resin and body wiring patterns 120. The dielectric layers 110 and the body wiring patterns 120 are stacked on one anther. The film substrate 200 is joined to one side of the body substrate 100, and includes a film 220, a mount wiring pattern 240, via holes 230, and a low elastic resin layer 210. The film 220 is made of a resin, such as polyimide. The mount wiring pattern 240 is formed on one side of the film 220 and an electric device is mounted on the mount wiring pattern 240. The via holes 230 electrically connect the body wiring pattern 120 and the mount wiring pattern 240. The low elastic resin layer 210 is formed between the body substrate 100 and the mount wiring pattern 240, and is made of a low elastic resin, which is less elastic than a dielectric layer 110 of the body substrate 100. Here, the low elastic resin includes a dispersed nitrile-butadiene rubber (NBR) thermoset modified epoxy resin sheet.
In the circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253, the low elastic resin layer 210 (i.e., resin layer having a small modulus of elasticity) easily deforms according to the stress caused by the thermal expansion of the mounted electric device and of the circuit substrate. Thus, the stress generated due to the difference of the coefficients of the thermal expansion between the electric device and the circuit substrate can be absorbed or mitigated.
However, in the circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253, a resin sheet is formed (provided) between the mount wiring pattern 240 and the body wiring pattern 120. Thus, when a crack is formed on a surface of the circuit substrate due to thermal stress and the like, the mount wiring pattern 240 may be electrically connected with the body wiring pattern 120. As a result, a dielectric property of the film substrate 200 may deteriorate, and breaking of the body wiring pattern 120 may occur.
Also, the circuit substrate disclosed in Japanese Unexamined Patent Publication No. 2001-36253 can be manufactured only through a build up method. As a result, even when a circuit substrate does not require minute patterning, a manufacturing process thereof tends to be complex.